1. Field of the Invention
The present invention relates to an apparatus and method of generating layout information, and, more particularly, to a layout information generating apparatus and method which generate information for writing ROM (Read Only Memory) codes and a mask option in a semiconductor integrated circuit incorporating a mask ROM.
2. Description of the Related Art
The background of the present invention will be discussed prior to a discussion of the related art. FIG. 1 is a diagram showing the structure for one bit of a 32-word ROM. Referring to FIG. 1, first, a description will be given of the structure of a ROM layout section which is the premise of the art relating to a layout information generating apparatus.
With reference to FIG. 1, of an address signal of five bits A.sub.0 to A.sub.4, A.sub.0 and A.sub.1 are input to an X decoder 32 to select one of select signal line X.sub.0 to X.sub.3 in the X-coordinate direction. Likewise, A.sub.2 to A.sub.4 in the 5-bit address signal A.sub.0 -A.sub.4 are input to an Y decoder 31 to select one of select signal lines Y.sub.0 to Y.sub.7 in the Y-coordinate direction. A ROM is constructed by laying out cell blocks 33 at the intersections of the thus constituted select signal lines in the X-coordinate direction and the Y-coordinate direction to set ROM cells, and leading out the existence/non-existence of each cell block 33 or ROM cell as a bit output B0.
In this case, whether the cell block 33 is laid out when a logic value is "1" or when it is "0" is determined by the circuit structure and the fabrication process. In the following description, it is assumed that the cell block 33 is laid out when a logic value is "1" and it is not when the logic value is "0." It is "ROM data" that is the original data of this layout and that has a sequence of "0" and "1" (for the length of the address). The ROM data is generally expressed by a hexadecimal (16) notation from the viewpoint of management.
A description will now be given of the structure of a mask option which is the premise of the art relating to a layout information generating apparatus. The "mask option" is an option which is the other portion than the ROM and which can be selected by a user. The mask option includes an option for whether or not a pull-up resistor is present, switching between pull-up and pull-down, etc. While this portion is intrinsically irrelevant to ROM data, the set value of the mask option is designated, together with input ROM data, in the case of a ROM-incorporated microcomputer product.
FIG. 2 is a diagram exemplifying the circuit structure of a part of a chip with a designated mask option portion. Referring to FIG. 2, a pull-up resistor 21 is preset, and it is determined if the pull-up resistor 21 should be reflected on the circuit, depending on whether or not a cell (hereinafter called "dummy cell") 22 is to be generated.
When the presence of the pull-up resistor is designated by a mask option designation field in an input ROM code, the dummy cell 22 is laid out and the pull-up resistor is reflected on the circuit as shown in FIG. 3. In the case of no pull-up resistor, the dummy cell 22 is not laid out and the pull-up resistor is not reflected on the circuit as shown in FIG. 4.
A description will now be given of the structure of a ROM definition and a mask option definition which are the premise of the art relating to a layout information generating apparatus.
Laying out ROM cells and dummy cells for the mask option in accordance with ROM data previously requires the position and coordinate information of the ROM cells and mask option dummy cells for an input address.
In the case of the ROM structure which has been discussed referring to FIG. 1, the position (select signal line) and coordinate information of ROM cells with respect to an input from the input address A.sub.0 -A.sub.4 as shown in, for example, FIG. 5.
The correlation shown in FIG. 5 is called a ROM definition which needs records by the number of ROM cells (one record consists of an address value and position information (select signal)). The memory capacity therefore becomes larger in proportion to the size of the ROM.
To reduce the memory capacity, an attempt has been made to compress a ROM definition by expressing the ROM definition in an array form by extracting and grouping ROM cells whose coordinate pitches and address pitches between adjoining ROM cells are identical.
Suppose that there is a ROM group consisting of 32 ROM cells as shown in FIG. 6. The numerals in the individual cells in the diagram are addresses associated with the ROM cells.
FIG. 7 illustrates the compression of a ROM definition in consideration of adjoining ROM cells. The ROM definition, which should originally need a total of 32 ROM cell records, is compressed to the size of three records. Referring to FIG. 7, the ROM definition consists of the definition of a reference point, the definition of the first array and the definition of the second array. The definition information of the reference point consists of the coordinates and address of the reference point and a bit, the first array definition includes level information (0), the direction (X direction), the pitch (X_p), the number (4), the address pitch (1) and the X-directional array, and the second array definition includes level information (1), the direction (Y direction), the pitch (Y_p), the number (8), the address pitch (4) and the Y-directional array.
In the actual layout, the contents of those definitions are used directly or after development.
Likewise, a mask option requires an associated address and the position and coordinate information of dummy cells, which are called a mask option definition. Since its correlation table and the like are the same as those for the ROM definition, their description will be omitted.
On the premise that the above-described related art is understood, first prior art will be discussed below. FIG. 8 is a block diagram showing the structure of the first prior art, and FIG. 9 is a flowchart for explaining a process sequence according to the first prior art. Referring to FIG. 8, this conventional apparatus comprises a PROM (Programmable ROM) reader 1, a ROM code input controller 2, a screen display controller 3, a display 4, a data processor 5, a layout information storage 6, a keyboard controller 7 and a keyboard 8.
The operation of the first prior art will be described with reference to the block diagram of FIG. 8, the flowchart of FIG. 9, the structural diagram for one bit of a ROM in FIG. 1 and the structural diagram of the pull-up resistor portion of a mask option in FIG. 2.
To begin with, assuming that all the ROM cells are laid out and all the dummy cells of a mask option are laid out, a designer analyzes the design of the circuits to be laid out and the layout pattern. With regard to the ROM section, the arrangement of the X decoder and Y decoder is analyzed for each bit output, and the address of each ROM cell and bit arrangement information are extracted as address signal values (step S301), as shown in FIG. 10.
Next, layout coordinate information is extracted based on the layout coordinates (X, Y) of a reference point 34 (see FIG. 1) as the reference point of one of ROM cells on the layout pattern, and the relative positional relationship among the individual ROM cells, which shows the distance from the reference point 34 computed from a pitch 35 (Y.sub.P) and a pitch 36 (X.sub.P) between ROM cells and the layout number, as shown in FIG. 11, (step S302). For example, information is extracted which indicates that a select signal line Y1 is selected when A.sub.4 and A.sub.3 in the address signal A.sub.4 -A.sub.0 are 0 and A.sub.2 is 1, and the Y coordinate of the ROM cell selected by this signal line Y.sub.1 is Y+Y.sub.P.
Subsequently, the designer associates the address bit arrangement information with coordinate information on the layout pattern for each ROM cell to prepare a table indicating bit outputs as shown in FIG. 12, and the table is supplied, together with a size 37 (Y.sub.N) and a size 38 (X.sub.S) of a cell block to be laid out, to the data processor 5 through the keyboard 8 (step S303).
With regard to an mask option, likewise, on the assumption that all the dummy cells are laid out, the designer performs the arrangement of the dummy cells of the mask option and extraction of the coordinates by referring to the design of the circuits to be laid out and the layout pattern (step S301').
Further, the extracted cell coordinates are associated with the address bit information of the associated ROM codes to prepare a correlation table (step S302'). This table is supplied, together with information indicating whether layout is carried out when the address associated bit is 0 or 1 and information on the cell block sizes (X.sub.m) and (Y.sub.m), to the data processor 5 through the keyboard 8 (step S303').
The PROM code reader 1 reads a target ROM code (same as "ROM data") via the ROM code input controller 2 (step S304), and the data processor 5 rearranges the read ROM code in the order of the address bit arrangement information of the individual ROM cells and the dummy cells of the mask option to be associated with one another (step S305).
Then, the logic value of the ROM code rearranged in the order of the address bit arrangement information is checked, and when and only when this logic value is "1," the cell block 33 whose size is designated based on the layout coordinate information of the associated ROM cell is generated as a layout pattern and is stored in the layout information storage 6 (step S306).
In this step S306, for the mask option, after the logic value of the ROM code is checked, it is determined whether the mask option designates layout for the logic value of "1" or for the logic value of "0." In the case of layout being made, a cell block whose size is designated based on the layout coordinate information of the associated dummy cell of the mask option is generated as a layout pattern and is stored in the layout information storage 6.
The processing results in step S306 are displayed on the display 4 for confirmation via the screen display controller 3 (step S307).
Next, a layout generating apparatus proposed in Unexamined Japanese Patent Publication No. Hei 5-314215 will be discussed as second prior art. The second prior art is a layout generating apparatus with an improvement made on the ROM layout information generation technique of the first prior art. FIG. 13 shows its structure in a block diagram. FIG. 14 is a flowchart for explaining a process sequence according to the second prior art.
Referring to FIG. 13, this second prior art comprises a PROM reader 1, a ROM code input controller 2, a screen display controller 3, a display 4, a data processor 5, a layout information storage 6, a keyboard controller 7, a keyboard 8, a ROM position information extractor 9, a layout inspecting section 12, and a logic simulation executing section 13. The operation of the second prior art will be discussed with reference to the block diagram of FIG. 13 and the flowchart of FIG. 14.
First, logic circuit diagram data is read in (step S401). Then, layout pattern data is read (step S402), and test pattern data is read (step S403). Further, a ROM code is read (step S404).
Next, the logic simulation executing section 13 prepares the address bit arrangement information of each ROM cell by using the read logic circuit diagram data, test pattern data and ROM code (step S405).
Then, the layout inspecting section 12 prepares the coordinate information of each ROM cell by using the logic circuit diagram data and layout pattern (step S406).
Then, the ROM position information extractor 9 associates the address bit arrangement information of each ROM cell with the coordinate information (step S407) and the associated address bit arrangement information and coordinate information are rearranged in the order of the address bit arrangement information in association with the ROM code (step S408).
When and only when the logic value of the rearranged ROM code is "1," a cell block with the size designated by a key operation on the keyboard 8 under the control of the keyboard controller 7 is separately output for the associated coordinates, so that the data processor 5 generates a layout pattern which is in turn stored in the layout information storage 6 (step S409). Then, the generated layout pattern is checked (step S410).
The second prior art differs from the first prior art in that the second prior art additionally comprises the ROM position information extractor 9, the layout inspecting section 12 and the logic simulation executing section 13 which are not included in the first prior art. This difference results in such an improvement that address bit arrangement information and coordinate information are automatically generated by the logic simulation and layout inspection.
The second prior art, however, has made no improvement on a mask option which has been discussed in the previous section of the first prior art.
Now, a mask pattern generating apparatus proposed in Unexamined Japanese Patent Publication No. Hei 6-215069 will be discussed as third prior art. This third prior art is a mask pattern generating apparatus with an improvement made on the ROM layout information generation technique of the first prior art. FIGS. 15 and 16 show the structure of the apparatus in a block diagram. FIG. 17 is a flowchart for explaining a process sequence of the third prior art. FIG. 17 is a flowchart associated with a process of extracting ROM coordinate information and acquiring associated ROM address information, and FIG. 16 is a diagram of a system structure with respect to FIG. 15.
Referring to FIGS. 15 and 16, this third prior art comprises a ROM coordinate extractor 106 for extracting ROM coordinate information from a chip layout data file 105, a ROM address information reader 107 which receives ROM address information, and a mask pattern generator 109 for generating a mask pattern based on chip layout data 1, ROM coordinate information extracted by the ROM coordinate extractor 106, ROM address information and ROM data from a ROM data file 108. The processing according to the third prior art will be discussed below with reference to the block diagrams of FIGS. 15 and 16 and the flowchart of FIG. 17.
In step S501, a CPU 102 receives a layout cell name. Then, the CPU 102 obtains, from chip layout data stored in a storage device 103, ROM coordinate information which has a layout cell name matching with the one received in step S501 (step S502). The CPU 102 also receives ROM address information corresponding to the ROM coordinate information (step S503). Then, the CPU 102 determines if the address information is adequate based on a layout cell repeat number included in the ROM coordinate information obtained in step S502 (step S504). When the address information is checked OK instep S504, the CPU 102 proceeds to step S505 to determine if there is any other layout cell whose address information should be received. When there is no such layout cell found in step S505, the entire processing is terminated.
A method of automatically extracting address information as a modification of the third prior art (see the second embodiment in the aforementioned Unexamined Japanese Patent Publication No. Hei 6-215069), will now be discussed by referring to the flowchart in FIG. 18.
In step S601, the CPU 102 receives the name of a layout cell which constitutes the memory array portion. The CPU 102 extracts ROM coordinate information m the chip layout data based on the layout cell name (step S602). The CPU 102 determines if any other layout cell is present (step S603). When there is a further layout cell in step S603 (Yes in step S603), the processes in steps S601 and S602 are repeated.
When there is no further layout cell found in step S603, the CPU 102 accepts an input of an address decoder name, extracts the circuit connection information of the decoder portion from the decoder name and chip layout data, and executes logic simulation using the circuit connection information to extract ROM address information (step S604).
Finally, the CPU 102 stores the ROM coordinate information and ROM address information in the storage device 103 and then terminates the processing.
The third prior art differs from the first prior art in that the third prior art additionally comprises the ROM coordinate extractor 106 and ROM address information reader 107, which are not included in the first prior art. The additional structure provides such an improvement that ROM coordinate information for an input cell is automatically generated.
The processing according to the third prior art, which has been discussed with reference to FIG. 18, has made an improvement in that ROM address information is automatically extracted from the input address decoder name and the chip layout data by performing logic simulation.
In the processing system which has been discussed with reference to FIG. 17, the second prior art, address information is input manually as done conventionally, and this third prior art has made no improvement on a mask option which has been discussed in the section of the first prior art.
As apparent from the above, the above-described prior arts have the following shortcomings.
(1) The first prior art requires a great number of processing steps and significant time and faces a possible occurrence of input errors resulting from manual processing.
This is because the first prior art requires that a designer should previously prepare and input arrangement information and coordinate information of ROM cells and arrangement information and coordinate information of a mask option.
(2) The second prior art, which is intended to make an improvement on the above problem (1) by using logic simulation and layout inspection, needs that for collation between a layout pattern and logic circuit diagram data, logic circuit diagram data which expresses the whole ROM portions by transistor devices should be prepared at the time of performing layout inspection. This disadvantageously requires a large number of processing steps.
More specifically, the ROM portion in a logic circuit diagram is generally described as a functional unit, not by logic symbols and transistor devices or the like. Further, logic simulation is carried out with the ROM portion developed on a memory as an arrangement (matrix) by the number of addresses having a length equivalent to the number of output bits, so that it is necessary to prepare logic circuit diagram data which expresses the ROM portion by transistor devices. Furthermore, logic simulation based on this logic circuit information requires a time, resulting in a considerable number of processing steps and processing time.
The second prior art is designed to execute logic simulation and layout inspection on the targeted ROM portion, and is not suitable for extraction of arrangement information and coordinate information of a mask option portion arranged on the whole chip. After all, like the first prior art, the second prior art necessitates extraction of arrangement information and coordinate information through manual processing.
(3) Like the first prior art, the third prior art, which additionally comprises the ROM coordinate extractor and ROM address information reader, faces a possible occurrence of input errors or the like caused by manual processing.
This is because while the third prior art automatically extracts the coordinate information of the ROM portion, it requires manual inputting of address information.
In the modification (second embodiment) of the third prior art which accomplishes automatic extraction of address information, address information is extracted from circuit diagram information and chip layout data. This method, as mentioned above, should execute the process by developing an arrangement (matrix) by the number of addresses having a length equivalent to the number of output bits on a memory and thus requires a considerable time.
The conventional method, which extracts address information from circuit diagram information and chip layout data by using logic simulation, extracts only the address and coordinates of the target ROM portion. With regard to the mask option portion, therefore, this method needs manual extraction of arrangement information and coordinate information as per the first prior art.